Datasheet · 1977
Data sheet for the faster 2112A family (250–450 ns), same 16-pin pinout as the 2112, with write-cycle timing for each speed grade. From Intel's 1977 Data Catalog, pages 2-72 to 2-76.
Data sheet for the faster 2112A family (250–450 ns), same 16-pin pinout as the 2112, with write-cycle timing for each speed grade. From Intel's 1977 Data Catalog, pages 2-72 to 2-76.
ll 2112A 256 X 4 BIT STATIC RAM 2112A-2 2112A 2112A-4 250 ns Max. 350 ns Max. 450 ns Max. • Single +5V Supply Voltage • Directly TTL Compatible: All Inputs and Outputs • Static MOS: No Clocks or Refreshing Required • Simple Memory Expansion: Chip Enable Input • Fully Decoded: On Chip Address Decode • Inputs Protected: All Inputs Have Protection Against Static Charge • Low Cost Packaging: 16 Pin Plastic Dual In-Line Configuration • Low Power: Typically 150 mW • Three-State Output: OR-Tie Capability The Intel® 2112A is a 256 word by 4-bit static random access memory element using N-channel MOS devices integrated on a monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate. The data is read out nondestructively and has the same polarity as the input data. Common input/output pins are provided. The 2112A is designed for memory applications in small systems where high performance, low cost, large bit storage, and simple interfacing are important design objectives. It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate chip enable (CE) lead allows easy selection of an individual package when outputs are OR-tied. The Intel® 2112A is fabricated with N-channel silicon gate technology. This technology allows the design and production of high performance, easy-to-use MOS circuits and provides a higher functional density on a monolithic chip than either conventional MOS technology or P-channel silicon gate technology. PIN CONFIGURATION LOGIC SYMBOL BLOCK DIAGRAM @ Ao AJ Vee A2 A, A, CE Ao As 1/04 A5 t/03 A1 1/02 GNO 1/01 ® ----o GND 110, A, WE A, ~Vee ., Ao ROW SELECT •2 1/02 A, 1103 AJ A, 1104 A4 MEMORY ARRAY 32 ROWS 32 COLUMNS As A, COLUMN 1/0 CIRCUITS A, 1/01 ® INPUT WE J/02 CE 1/03 DATA CONTROL ® ® 0 As A5 A7 1/04 PIN NAMES ~-A 7 _ A~~RESS INPU_~~ WE WRITE ENABLE CE CHIP ENABLE INPUT __ ~ -CE @ 0 · PIN NUMBERS l/0)_-110_4 DAT~ INPUT/OUTPUT__ _, VC'.~ POWER (+5V) ~® ____! WE 2-72 2112A FAMILY *COMMENT: ABSOLUTE MAXIMUM RATINGS* Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient Temperature Under Bias ..... -10°C to 80°C Storage Temperature . . . . . . . . . . . -65°C to +150°C Voltage On Any Pin With Respect to Ground . . . . . . . . . -0.5V to +7V Power Dissipation . . . . . . . . . . . . . . . . . . . . 1 Watt D.C. AND OPERATING CHARACTERI STICS TA= 0°C to 70°C, Vee= 5V ±5% unless otherwise specified. lu Typ.1 11 Min. Parameter Symbol Unit Test Conditions Input Current 1 10 µA V1N = 0 to 5.25V 1/0 Leakage Current 1 10 µA Output Disabled, V110=4.0V 1/0 Leakage Current -1 -10 Power Supply Current 55 35 2112A, 2112A-4 ----=2:-:1--:1-=2..,.A""'-2:-+---t------:4-=-5-+-"""6-=-5--I Power Supply Current 2112A, 2112A-4 2112A-2 60 70 µA Output Disabled, V110=0.45V mA V1N = 5.25V, 1110 = OmA TA= 25°C mA V1N = 5.25V, 1110 = OmA TA= 0°C Input "Low" Voltage -0.5 0.8 v Input "High" Voltage 2.0 Vee +0.45 v v Output "Low" Voltage Output "High" VoH Max. 2112A-4 Voltage loL = 2.0 mA v v 2112A, 2112A-2 2.4 loH = -200µA loH = -150µA A.C. CHARACTER ISTICS FOR 2112A-2 READ CYCLE Symbol TA = 0°C to 70°C, Vee = 5V ±5% unless otherwise specified. Parameter Typ_l1l Min. Max. Unit Test Conditions ns tr, t 1 = 20ns 250 tRc Read Cycle tA Access Time tea Chip Enable To Output Time tco Chip Enable To Output Disable Time 0 toH Previous Read Data Valid After Change of Address 40 250 ns 180 ns Timing Reference= 1.5V 120 ns Load= 1 TTL Gate ns and CL= 100pF. READ CYCLE WAVEFORMS [2] CAPACITANC E TA= 25°C, f = 1 MHz - - - - - - tA - - - - - - - ADDRESS Symbol Test Limits (pF) Typ.[1] Max. C1N Input Capacitance (All Input Pins) V1N = OV 4 8 C110 1/0 Capacitance V110 = OV 10 15 NOTES: 1. Typical values are for TA= 25° C and nominal supply voltage. 2. This parameter is periodically sampled and is not 100% tested. 2-73 2112A FAMILY A.C. CHARACTERI STICS FOR 2112A-2 (Continued) WRITE CYCLE #1 Symbol TA = 0°C to 70°C, Vee= 5V ±5% Parameter Min. Typ.!1l Max. Unit Test Conditions twe1 Write Cycle 200 ns tAW1 Address To Write Setup Time 20 ns tr, t1 = 20ns Input Levels = 0.8V or 2.0V tow1 Write Setup Time 180 ns Timing Reference= 1.5V twp1 Write Pulse Width 180 ns Load = 1 TTL Gate tcs1 Chip Enable Setup Time 0 ns teH1 Chip Enable Hold Time 0 ns twR1 Write Recovery Time 0 ns toH1 Data Hold Time 0 ns tew1 Chip Enable To Write Setup Time 180 ns and CL = lOOpF. WRITE CYCLE #2 TA= 0°C to 70°C, Vee= 5V ±5% Symbol twe2 Parameter Typ,!1l Min. Write Cycle Max. Unit Test Conditions 320 ns tAW2 Address To Write Setup Time 20 ns tr. t1 = 20ns Input Levels= 0.8V or 2.0V tow2 Write Setup Time 180 ns Timing Reference= 1.5V two2 Write To Output Disable Time 120 ns Load = 1 TTL Gate tcs2 Chip Ena_ble Setup Time 0 ns teH2 Chip Enable Hold Time 0 ns twR2 Write Recovery Time 0 ns toH2 Data Hold Time 0 ns and CL = lOOpF. WRITE CYCLE WAVEFORMS WRITE CYCLE #1 WRITE CYCLE #2 . . - - - - - - - twc1 --~-~----ADDRESS _ ___ -tcH1__,_ INPUT/OUTPUT DATA IN INPUT/OUTPUT STABLE two2- NOTE: 1. Typical values are for TA= 25°e and nominal supply voltage. 2-74 2112A FAMILY A.C. CHARACTERI STICS FOR 2112A READ CYCLE TA = 0°C to 70°C, Vee= 5V ±5% unless otherwise specified. Parameter Symbol tRe tA teo teo toH Read Cycle Access Time Chip Enable To Output Time Chip Enable To Output Disable Time 350 Previous Read Data Valid After Change of Address 40 WRITE CYCLE #1 Symbol Min. Typ.l1l 0 Max. Unit Test Conditions ns tr. t1 = 20ns Input Levels= O.BV or 2.0V 350 240 ns ns 200 ns ns Load= 1 TTL Gate Unit Test Conditions Timing Reference= 1.5V and CL= 100pF. TA = 0°C to 70°C, Vee= sv ±5% Parameter Min. Typ.[1] Max. ns tr, t1 = 20ns twe1 tAW1 Write Cycle 270 Address To Write Setup Time 20 ns Input Levels= O.BV or 2.0V tow1 twp1 250 ns Timing Reference = 1.5V 250 0 ns Load= 1 TTL Gate tes1 Write Setup Time Write Pulse Width Chip Enable Setup Time teH1 Chip Enable Hold Time 0 ns twR1 Write Recovery Time Data Hold Time 0 ns tDH1 0 ns tew1 Chip Enable to Write Setup Time 250 ns ns and CL= 100pF. WRITE CYCLE #2 TA = 0°C to 70°C, Vee = 5V ±5% Symbol twe2 tAW2 tow2 two2 Min. 470 20 Typ.l1J Max. Unit ns Test Conditions ns tr, t1 = 20ns Input Levels= O.BV or 2.0V 250 ns Timing Reference= 1.5V 200 0 ns ns Load= 1 TTL Gate 0 ns teH2 Chip Enable Setup Time Chip Enable Hold Time twR2 Write Recovery Time 0 ns toH2 Data Hold Time 0 ns tes2 NOTE: Parameter Write Cycle Address To Write Setup Time Write Setup Time Write To Output Disable Time 1. Typical values are for TA= 25°e and nominal supply voltage. 2-75 and CL = 100pF. ll 2112A FAMILY A.C. CHARACTERI STICS FOR 2112A-4 READ CYCLE TA = D°C to 7D°C, Vee = 5V ±5% unless otherwise specified. Symbol Parameter Min. Typ_[lJ Max. Unit Test Conditions ns t,, t1 = 2Dns tRe Read Cycle tA Access Time 45D ns Input Levels= D.8V or 2.DV teo Chip Enable To Output Time Chip Enable To Output Disable Time 310 ns Timing Reference= 1.5V ns Load= 1 TTL Gate teo toH Previous Read Data Valid After Change of Address WRITE CYCLE #1 Symbol twe1 tAW1 toW1 45D D 26D ns 4D and CL = 100pF. TA = D°C to 70°C, Vee= 5V ±5% Parameter Write Cycle Min. Typ.[1) Max. Unit Test Conditions ns t,, t 1 = 20ns ns ns Input Levels= 0.8V or 2.DV Timing Reference= 1.5V ns Load = 1 TTL Gate Address To Write Setup Time 32D 2D Write Setup Time 300 twp1 Write Pulse Width tes1 Chip Enable Setup Time 3DO 0 ns teH1 Chip Enable Hold Time D ns ns twR1 Write Recovery Time 0 toH1 Data Hold Time D ns tew1 Chip Enable to Write Setup Time 3DD ns and CL= 10DpF. WRITE CYCLE #2 TA = 0°C to 70°C, Vee= 5V ±5% Symbol NOTE: twe2 tAW2 tow2 Parameter Write Cycle Min. Typ}1l Max. Unit Test Conditions ns t,. t 1 = 2Dns Address To Write Setup Time 580 2D ns Input Levels= 0.8V or 2.DV Write Setup Time 30D ns Timing Reference= 1.5V ns Load = 1 TTL Gate two2 Write To Output Disable Time tes2 Chip Enable Setup Time 26D 0 teH2 Chip Enable Hold Time 0 ns ns twR2 Write Recovery Time 0 ns toH2 Data Hold Time D ns 1. Typical values are for TA= 25°e and nominal supply voltage. 2-76 and CL= 100pF.