Datasheet · 1976
The original 2112 data sheet (pages 2-77 to 2-80 of Intel's 1976 Data Catalog): pinout, DC characteristics and read/write timing. The 2112-2 (650 ns) is the RAM in the Heathkit ET-3400 trainer.
The original 2112 data sheet (pages 2-77 to 2-80 of Intel's 1976 Data Catalog): pinout, DC characteristics and read/write timing. The 2112-2 (650 ns) is the RAM in the Heathkit ET-3400 trainer.
infer 2112,2112-2 1024 BIT (256 x 4) STATIC MOS RAM WITH COMMON DATA I/O • Organization 256 Words by 4 Bits • Common Data Input and Output • Single +5V Supply Voltage • Directly TTL Compatible: All Inputs and Output • Static MOS: No Clocks or Refreshing Required • Access Time: 0.65 to 1 fJsec Max. • Simple Memory Expansion: Chip Enable Input • Fully Decoded: On Chip Address Decode • Inputs Protected: All Inputs Have Protection Against Static Charge • Low Cost Packaging: 16 Pin Plastic Dual In-Line Configuration • Low Power: Typically 150mW • Three-State Output: OR-Tie Capability The Intel® 2112 is a 256 word by 4-bit static random access memory element using normally off N-channel MOS devices integrated on a monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate. The data is read out non-destructively and has the same polarity as the input data. Common input/output pins are provided. The 2112 is designed for memory applications in small systems where high performance, low cost, large bit storage, and simple interfacing are important design objectives. It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate chip enable (CE) lead allows easy selection of an individual package when outputs are OR-tied. The Intel® 2112 is fabricated with N-channel silicon gate technology. This technology allows the design and production of high performance, easy-to-use MOS circuits and provides a higher functional density on a monolithic chip than either conventional MOS technology or P-channel silicon gate technology. Intel's silicon gate technology also provides excellent protection against contamination. This permits the use of low cost silicone packaging. PIN CONFIGURATION A, A, 1/°3 0 ® ® A, CD A, A4 1/°4 A4 @ Ao Vee Ao A4 A, I/O, A, R/W A, 1/°2 Ao CE A2 BLOCK DIAGRAM LOGIC SYMBOL As 1/0 4 As I/O, As A, 1/°2 GND 1/01 -Vee A, ROW SELECT MEMORY ARRAY ® -GND 32 ROWS 32 COLUMNS @ 2112 As A, INPUT DATA CONTROL R/W CE PIN NAMES Ao'A, ADDRESS INPUTS R/W READ/WRITE INPUT CE CHIP ENABLE INPUT 0= PIN NUMBERS 110,.11°4 DATA INPUTIOUTPUT Vee POWER 1+5VJ_~ 2-77 2112, 2112-2 'COMMENT: Absolute Maximum Ratings* Stresses above those listed under ''Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient Temperature Under Bias ...... O°C to 70° C Storage Temperature . . . . . . . . . . . _65°C to +150°C Voltage On Any Pin With Respect to Ground. . . . . . . .. -0.5V to +7V Power Dissipation .. . . . . . . . . . . . . . . . . .. 1 Watt D.C. and Operating Characteristics for 2112, 2112-2 T A = O°C to 70°C, Vee = 5V ±5% unless otherwise specified. Symbol Parameter Typ.[l] Min. Max. Unit Test Conditions VIN = 0 to 5.25V III Input Current 10 flA ILOH I/O Leakage Current flA CE = 2.2V, VI/a = 4.0V ILOL I/O Leakage Current 15 -50 CE = 2.2V, Vila = 0.45V ICCI Power Supply Current 60 flA mA ICC2 Power Supply Current 70 mA V V 30 VIL Input "Low" Voltage -0.5 +0.65 VIH VOL VOH Input "High" Voltage Output "Low" Voltage Output "High" Voltage 2.2 Vee +0.45 VIN = 5.25V, 1110 = OmA TA = 25°C VIN = 5.25V, 1110 = OmA TA = O°C V V 2.2 10L = 2mA 10H = -150flA A.C. Characteristics for 2112 READ CYCLE Symbol T A = O°c to 70°C, Vee = 5V ±5% unless otherwise specified. Parameter Read Cycle Min. Typ,lll Max. 1,000 tRe tA Access Time teo Chip Enable To Output Time teD Chip EnableTo Output Disable Time 0 tOH Previous Read Data Valid After Change of Add ress 40 Unit Test Conditions ns t r , tf = 20ns ns 1,000 800 ns VIN = +0.65V to +2.2V Timing Reference = 1.5V 200 ns Load = 1 TTL Gate ns and CL = 100pF. READ CYCLE WAVEFORMS [2] Capacitance· TA = 25°C, f = 1 MHz Symbol Test Limits (pF) Typ.[l] Max. CIN Input Capacitance (All Input Pins) VIN = OV 4 8 CI/O I/O Capacitance VI/a = OV 10 15 NOTES: 1. Typical values are for TA = 25° e and nominal supply voltage. 2. This parameter is periodically sampled and is not 100% tested. :2-78 2112, 2112-2 A.C. Characteristics for 2112 (Continued) WRITE CYCLE #1 TA = o°c to 70°C, Vcc = 5V ±5% Symbol Parameter Typ.!11 Min. Unit Test Conditions 850 ns t r , tf = 20ns Address To Write Setup Time 150 ns Write Setup Time 650 ns VIN = +0.65V to +2.2V Timing Reference = 1.5V Write Pulse Width 650 ns Load = 1 TTL Gate Chip Enable Setup Time 0 ns tCHl Chip Enable Hold Time 0 ns tWRl Write Recovery Time 50 ns tOHl Data Hold Time 100 ns tCWl Chip Enable To Write Setup Time 650 ns tWCl Write Cycle tAWl tOWl tWPl tCSl Max. and CL = HlOpF. WRITE CYCLE #2 TA = O°C to 70°C, VCC = 5V ±5% Symbol Parameter Typ .l1 1 Min. Max. Unit Test Conditions tWC2 Write Cycle 1050 ns t r , tf = 20ns tAW2 tOW2 Address To Write Setup Time 150 650 ns Write Setup Time ns VIN = +0.65V to +2.2V Timing Reference = 1.5V Load = 1 TTL Gate tW02 Write To Output Disable Time 200 ns tCS2 Chip Enable Setup Time 0 ns tCH2 Chip Enable Hold Time 0 ns tWR2 Write Recovery Time 50 ns tOH2 Data Hold Time 100 ns and CL = 100pF. Write Cycle Waveforms WRITE CYCLE #1 WRITE CYCLE #2 .... t A W 1 - - t W P 1 - - t w R l - NOTE: 1. Typical values are for TA = 25°C and nominal supply voltage. 2-79 2112, 2112-2 2112-2 (650 ns Access Time) A.C. Characteristics for 2112-2 READ CYCLE TA = o°c to lOoC, Vcc = 5V ±5% unless otherwise specified. Symbol Parameter tRC Read Cycle tA Access Time tco tco Chip Enable To Output Time Chip Enable To Output Disable Time tOH Previous Read Data Valid After Change of Address WRITE CYCLE #1 Min. TypJ1] Max. 650 650 500 150 0 Unit Test Conditions ns t" tf = 20ns ns ns Timing Reference = 1.5V ns ns 40 VIN =+0.65V to +2.2V Load = 1 TTL Gate and CL = 100pF. TA = O°C to lO°C, Vcc = 5V ±5% Typ.[1] Unit Test Conditions tWCl tAWl tOWl Write Cycle 500 ns t r , tf - 20ns Address To Write Setup Time ns VIN =+0.65V to +2.2V Write Setup Time 100 280 ns Timing Reference = 1.5V tWPl Write Pulse Width 350 ns Load = 1 TTL Gate tCSl Chip Enable Setup Time 0 ns tCHl Chip Enable Hold Time 0 ns tWRl Write Recovery Time 50 tOHl Data Hold Time 50 ns ns tCWl Chip Enable to Write Setup Time 350 ns Symbol Parameter Min. Max. and CL = 100pF. 1 WRITE CYCLE #2 TA = O°C to lO°C, VCC = 5V ±5% NOTE: 2-80 T yp Jl] Unit Test Conditions 650 100 ns t r , tf - 20ns ns VIN =+0.65V to +2.2V ns Timing Reference = 1.5V ns Load = 1 TTL Gate Chip Enable Setup Time 280 200 0 tCH2 Chip Enable Hold Time 0 ns tWR2 Write Recovery Time 50 ns tOH2 Data Hold Time 50 ns Symbol Parameter tWC2 tAW2 Write Cycle tOW2 Write Setup Time tW02 Write To Output Disable Time tCS2 Address To Write Setup Time Min. 1. Typical values are for TA = 25° C and nominal supply voltage. Max. ns and CL = 100pF.